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| -1- NJU6655 ver.2004-03-05 preliminary 64-common x 160-segment + 1-icon common bitmap lcd driver general description the NJU6655 is a bitmap lcd driver to display graphics or characters. it contains 10,400 bits display data ram, microprocessor interface circuits, instruction decoder, 64-common and 160-segment + 1-icon-common drivers. the bit image display data is transferred to the display data ram by serial or 8-bit parallel interface. 65 x 160 dots graphics or 10-character 4-line by 16 x 16 dots character with icon are displayed by NJU6655 itself. the wide operating voltage from 2.4 to 5.5v and low operating current are suitable for battery-powered applications. the build-in electrical variable resistance is very precision, furthermore the rectangle outlook is very applicable to cog or slim tcp. features direct correspondence between display data ram and lcd pixel display data ram - 10,400 bits 225 lcd drivers - 64-common and 160-segment + 1-icon common direct microprocessor interface for both of 68 and 80 type mpu serial interface (si, scl, a0, cs 1 b, cs 2 ) programmable bias selection : 1/5,1/7,1/9 bias useful instruction set display on/off cont, initial display line set, page address set, column address set, status read, display data read/write, adc select, inverse display, entire display on/off, bias select, read modify write, end, reset, common direction register set, power control set, feedback resistor ratio set, evr mode set, evr register set, static indicator on/off, static indicator register set, power save, power save reset, n-line inverse drive register set, n-line inverse drive reset, partial select, internal oscillation circuit on. power supply circuits for lcd incorporated voltage booster circuits (4-time maximum), voltage adjust circuits, voltage follower x 4 voltage regulator incorporated precision electrical variable resistance (64-step) low power consumption t.b.d.ua(typ.). operating voltage (all the voltages are based on v dd =0v.) - logic operating voltage : -2.4v to -5.5v - voltage booster operating voltage : -2.4v to -6.0v - lcd driving voltage : -4.5v to -18.0v rectangle outlook for cog package outline : bump-chip c-mos technology (substrate : n) package outline NJU6655cj
- 2 - NJU6655 ver.2004-03-05 pad location chip center : x=0um, y=0um chip size : x=8.88mm,y=2.77mm chip thickness : 675um 30um bump size : 130um x 31um bump pitch : 50um(min.) bump height : 17.5um(typ.) bump material : au voltage boosting polarity : negative voltage (v dd common) substrate : n frs test 1 v ss wrb v ss rdb d 0 v dd d 1 d 3 d 2 d 4 d 6 (scl) d 5 d 7 (si) v dd v dd v dd v dd v dd v ss v ss2 v ss v ss2 v ss2 v ss2 v ss2 v out v out c3 - c1 + c3 - c1 + c1 - c1 - c2 - c2 + c2 - c2 + v ss v ss v rs v dd v rs v dd v 1 v 1 v 2 v 3 v 2 v 3 v 4 v 4 v 5 vr v 5 v dd cls m/s v ss p/s c86 s 155 s 3 s 4 dofb cl sync cs 1 b v ss cs 2 resb v dd a0 sync fr dummy 2 dummy 19 v dd dummy 16 dummy 1 s 157 s 158 t.b.d. v ss test 2 irs dummy 5 v dd dummy 6 s 156 c 32 c 33 s 159 dummy 3 dummy 4 comm c 63 dummy 23 dummy 26 dummy 25 dummy 24 dummy 22 dummy 21 dummy 20 s 2 s 1 comm c 0 s 0 c 31 c 30 dummy 10 dummy 7 dummy 8 dummy 9 dummy 11 dummy 12 dummy 13 dummy 15 dummy 14 dummy 18 dummy 17 y x -3- NJU6655 ver.2004-03-05 pad coordinates chip size 8.88 x 2.77mm(chip center x=0um, y=0um) pad no. terminal x= um y= um pad no. terminal x= um y= um 1 dummy 1 -4092 -1213 51 c2 + 1622 -1213 2 dummy 2 -4042 -1213 52 c2 + 1672 -1213 3 test 1 -3919 -1213 53 v ss 1722 -1213 4 sync -3796 -1213 54 v ss 1772 -1213 5 frs -3637 -1213 55 v rs 1822 -1213 6 fr -3417 -1213 56 v rs 1872 -1213 7 cl -3197 -1213 57 dummy 3 1922 -1213 8 dofb -2976 -1213 58 dummy 4 1972 -1213 9 sync -2756 -1213 59 v dd 2022 -1213 10 v ss -2598 -1213 60 v dd 2072 -1213 11 cs 1 b -2474 -1213 61 v 1 2122 -1213 12 cs 2 -2317 -1213 62 v 1 2172 -1213 13 v dd -2194 -1213 63 v 2 2222 -1213 14 resb -2071 -1213 64 v 2 2272 -1213 15 a0 -1914 -1213 65 v 3 2322 -1213 16 v ss -1790 -1213 66 v 3 2372 -1213 17 wrb -1667 -1213 67 v 4 2422 -1213 18 rdb -1510 -1213 68 v 4 2472 -1213 19 v dd -1387 -1213 69 v 5 2522 -1213 20 d 0 -1229 -1213 70 v 5 2572 -1213 21 d 1 -1008 -1213 71 vr 2622 -1213 22 d 2 -788 -1213 72 v dd 2672 -1213 23 d 3 -567 -1213 73 m/s 2796 -1213 24 d 4 -347 -1213 74 cls 2953 -1213 25 d 5 -127 -1213 75 v ss 3076 -1213 26 d 6 (scl) 94 -1213 76 c86 3199 -1213 27 d 7 (si) 314 -1213 77 p/s 3356 -1213 28 v dd 472 -1213 78 v dd 3480 -1213 29 v dd 522 -1213 79 test 2 3603 -1213 30 v dd 572 -1213 80 v ss 3726 -1213 31 v dd 622 -1213 81 irs 3849 -1213 32 v dd 672 -1213 82 v dd 3972 -1213 33 v ss 722 -1213 83 dummy 5 4022 -1213 34 v ss 772 -1213 84 dummy 6 4072 -1213 35 v ss 822 -1213 85 dummy 7 4265 -1037 36 v ss2 872 -1213 86 dummy 8 4265 -987 37 v ss2 922 -1213 87 dummy 9 4265 -937 38 v ss2 972 -1213 88 dummy 10 4265 -887 39 v ss2 1022 -1213 89 c 31 4265 -837 40 v ss2 1072 -1213 90 c 30 4265 -787 41 v out 1122 -1213 91 c 29 4265 -737 42 v out 1172 -1213 92 c 28 4265 -687 43 c3 - 1222 -1213 93 c 27 4265 -637 44 c3 - 1272 -1213 94 c 26 4265 -587 45 c1 + 1322 -1213 95 c 25 4265 -537 46 c1 + 1372 -1213 96 c 24 4265 -487 47 c1 - 1422 -1213 97 c 23 4265 -437 48 c1 - 1472 -1213 98 c 22 4265 -387 49 c2 - 1522 -1213 99 c 21 4265 -337 50 c2 - 1572 -1213 100 c 20 4265 -287 - 4 - NJU6655 ver.2004-03-05 pad no. terminal x= um y= um pad no. terminal x= um y= um 101 c 19 4265 -237 151 s 23 2965 1213 102 c 18 4265 -187 152 s 24 2915 1213 103 c 17 4265 -137 153 s 25 2865 1213 104 c 16 4265 -87 154 s 26 2815 1213 105 c 15 4265 -37 155 s 27 2765 1213 106 c 14 4265 13 156 s 28 2715 1213 107 c 13 4265 63 157 s 29 2665 1213 108 c 12 4265 113 158 s 30 2615 1213 109 c 11 4265 163 159 s 31 2565 1213 110 c 10 4265 213 160 s 32 2515 1213 111 c 9 4265 263 161 s 33 2465 1213 112 c 8 4265 313 162 s 34 2415 1213 113 c 7 4265 363 163 s 35 2365 1213 114 c 6 4265 413 164 s 36 2315 1213 115 c 5 4265 463 165 s 37 2265 1213 116 c 4 4265 513 166 s 38 2215 1213 117 c 3 4265 563 167 s 39 2165 1213 118 c 2 4265 613 168 s 40 2115 1213 119 c 1 4265 663 169 s 41 2065 1213 120 c 0 4265 713 170 s 42 2015 1213 121 comm 4265 763 171 s 43 1965 1213 122 s 0 4265 813 172 s 44 1915 1213 123 s 1 4265 863 173 s 45 1865 1213 124 s 2 4265 913 174 s 46 1815 1213 125 dummy 11 4265 963 175 s 47 1765 1213 126 dummy 12 4265 1013 176 s 48 1715 1213 127 dummy 13 4265 1063 177 s 49 1665 1213 128 dummy 14 4115 1213 178 s 50 1615 1213 129 dummy 15 4065 1213 179 s 51 1565 1213 130 dummy 16 4015 1213 180 s 52 1515 1213 131 s 3 3965 1213 181 s 53 1465 1213 132 s 4 3915 1213 182 s 54 1415 1213 133 s 5 3865 1213 183 s 55 1365 1213 134 s 6 3815 1213 184 s 56 1315 1213 135 s 7 3765 1213 185 s 57 1265 1213 136 s 8 3715 1213 186 s 58 1215 1213 137 s 9 3665 1213 187 s 59 1165 1213 138 s 10 3615 1213 188 s 60 1115 1213 139 s 11 3565 1213 189 s 61 1065 1213 140 s 12 3515 1213 190 s 62 1015 1213 141 s 13 3465 1213 191 s 63 965 1213 142 s 14 3415 1213 192 s 64 915 1213 143 s 15 3365 1213 193 s 65 865 1213 144 s 16 3315 1213 194 s 66 815 1213 145 s 17 3265 1213 195 s 67 765 1213 146 s 18 3215 1213 196 s 68 715 1213 147 s 19 3165 1213 197 s 69 665 1213 148 s 20 3115 1213 198 s 70 615 1213 149 s 21 3065 1213 199 s 71 565 1213 150 s 22 3015 1213 200 s 72 515 1213 -5- NJU6655 ver.2004-03-05 pad no. terminal x= um y= um pad no. terminal x= um y= um 201 s 73 465 1213 251 s 123 -2035 1213 202 s 74 415 1213 252 s 124 -2085 1213 203 s 75 365 1213 253 s 125 -2135 1213 204 s 76 315 1213 254 s 126 -2185 1213 205 s 77 265 1213 255 s 127 -2235 1213 206 s 78 215 1213 256 s 128 -2285 1213 207 s 79 165 1213 257 s 129 -2335 1213 208 s 80 115 1213 258 s 130 -2385 1213 209 s 81 65 1213 259 s 131 -2435 1213 210 s 82 15 1213 260 s 132 -2485 1213 211 s 83 -35 1213 261 s 133 -2535 1213 212 s 84 -85 1213 262 s 134 -2585 1213 213 s 85 -135 1213 263 s 135 -2635 1213 214 s 86 -185 1213 264 s 136 -2685 1213 215 s 87 -235 1213 265 s 137 -2735 1213 216 s 88 -285 1213 266 s 138 -2785 1213 217 s 89 -335 1213 267 s 139 -2835 1213 218 s 90 -385 1213 268 s 140 -2885 1213 219 s 91 -435 1213 269 s 141 -2935 1213 220 s 92 -485 1213 270 s 142 -2985 1213 221 s 93 -535 1213 271 s 143 -3035 1213 222 s 94 -585 1213 272 s 144 -3085 1213 223 s 95 -635 1213 273 s 145 -3135 1213 224 s 96 -685 1213 274 s 146 -3185 1213 225 s 97 -735 1213 275 s 147 -3235 1213 226 s 98 -785 1213 276 s 148 -3285 1213 227 s 99 -835 1213 277 s 149 -3335 1213 228 s 100 -885 1213 278 s 150 -3385 1213 229 s 101 -935 1213 279 s 151 -3435 1213 230 s 102 -985 1213 280 s 152 -3485 1213 231 s 103 -1035 1213 281 s 153 -3535 1213 232 s 104 -1085 1213 282 s 154 -3585 1213 233 s 105 -1135 1213 283 s 155 -3635 1213 234 s 106 -1185 1213 284 s 156 -3685 1213 235 s 107 -1235 1213 285 dummy 17 -4015 1213 236 s 108 -1285 1213 286 dummy 18 -4065 1213 237 s 109 -1335 1213 287 dummy 19 -4115 1213 238 s 110 -1385 1213 288 dummy 20 -4265 1063 239 s 111 -1435 1213 289 dummy 21 -4265 1013 240 s 112 -1485 1213 290 dummy 22 -4265 963 241 s 113 -1535 1213 291 s 157 -4265 913 242 s 114 -1585 1213 292 s 158 -4265 863 243 s 115 -1635 1213 293 s 159 -4265 813 244 s 116 -1685 1213 294 c 32 -4265 763 245 s 117 -1735 1213 295 c 33 -4265 713 246 s 118 -1785 1213 296 c 34 -4265 663 247 s 119 -1835 1213 297 c 35 -4265 613 248 s 120 -1885 1213 298 c 36 -4265 563 249 s 121 -1935 1213 299 c 37 -4265 513 250 s 122 -1985 1213 300 c 38 -4265 463 - 6 - NJU6655 ver.2004-03-05 pad no. terminal x= um y= um 301 c 39 -4265 413 302 c 40 -4265 363 303 c 41 -4265 313 304 c 42 -4265 263 305 c 43 -4265 213 306 c 44 -4265 163 307 c 45 -4265 113 308 c 46 -4265 63 309 c 47 -4265 13 310 c 48 -4265 -37 311 c 49 -4265 -87 312 c 50 -4265 -137 313 c 51 -4265 -187 314 c 52 -4265 -237 315 c 53 -4265 -287 316 c 54 -4265 -337 317 c 55 -4265 -387 318 c 56 -4265 -437 319 c 57 -4265 -487 320 c 58 -4265 -537 321 c 59 -4265 -587 322 c 60 -4265 -637 323 c 61 -4265 -687 324 c 62 -4265 -737 325 c 63 -4265 -787 326 comm -4265 -837 327 dummy 23 -4265 -887 328 dummy 24 -4265 -937 329 dummy 25 -4265 -987 330 dummy 26 -4265 -1037 -7- NJU6655 ver.2004-03-05 block diagram c 31 - - - - c 0 c 32 - - - c 63 s 0 - - - - - - - - - - - - - s 159 comm v ss v dd v 1 to v 5 c1 + /c1 - c2 + /c2 - c3 - v out v ss2 cs 2 a0 c86 d 7 (si) d 6 (scl) d 0 to d 5 resb cs 1 b wrb rdb reset mpu interface instruction decoder status busy flag bus holder internal bus line multiplexer column address register 8bit column address counter 8bit column address decoder 160 page address register oscillator display timing line counter line address decoder low address decoder common direction display data ram 160 x 65 = 10,400-bit display data latch segment drivers common drivers shift register shift register vo l t a g e converter common timing dofb vo l t a g e followers internal power circuits m/s fr cl sync frs cls common drivers initial display line 5 comm i/o buffer p/s v rs vr irs vo l t a g e regulator - 8 - NJU6655 ver.2004-03-05 terminal discription no. symbol i/o function 1,2,57,58, 83 to 88, 125 to 130, 2 85 to 290, 327 to 330 dummy 1 to dummy 26 dummy terminals. these are open terminals electrically. 13,19, 2 8 to 32 59,60,72, 78,82 v dd power power supply terminal. 10,16, 33 to 35 53,54,75, 80 v ss gnd ground terminal. 36 to 40 v ss2 power reference voltage for voltage booster. 55,56 v rs power external reference voltage input terminal. normally open. lcd driving voltage supplying terminal. when the internal voltage booster is not used, supply each level of lcd driving voltage from outside with following relation. v dd v 1 v 2 v 3 v 4 v 5 v out when the internal power supply is on, the internal circuits generate and supply following lcd bias voltage from v 1 to v 4 terminal. bias v 1 v 2 v 3 v 4 1/5 bias v 5 +4/5v lcd v 5 +3/5v lcd v 5 +2/5v lcd v 5 +1/5v lcd 1/7 bias v 5 +6/7v lcd v 5 +5/7v lcd v 5 +2/7v lcd v 5 +1/7v lcd 1/9 bias v 5 +8/9v lcd v 5 +7/9v lcd v 5 +2/9v lcd v 5 +1/9v lcd 61,62 63,64 65,66 67,68 69,70 v 1 v 2 v 3 v 4 v 5 power (v lcd =v dd -v 5 ) 4 5,46 4 7,48 51,52 4 9,50 4 3,44 c1 + c1 - c2 + c2 - c3 - o boosted capacitor connecting terminals used for voltage booster. 4 1,42 v out o voltage booster output terminal. connect the boosted capacitor between this terminal and v ss2 . 71 vr i voltage adjustment terminal connect external feedback resistor to control the lcd driving voltage v5. this terminal is effective when irs=?l?. 2 0 to 27 (26, 27) d 0 to d 7 (scl, si) i/o data input/output terminals. p/s="h" : tri-state bi-directional data i/o terminal in 8-bit parallel operation. p/s="l" : d 7 =serial data input terminal. d 6 =serial data clock signal input terminal. d 0 to d 5 terminals are hi-impedance. data from si is loaded at the rising edge of scl and latched as the parallel data at 8th rising edge of scl. when cs 1 b="h", d 0 to d 7 terminals are hi-impedance. data discrimination signal input terminal. connect to the address bus of mpu. the data on the d 0 to d 7 is distinguished between display data and instruction by status of a0. a0 h l distinction display data instruction 15 a0 i 14 resb i reset terminal. when the resb terminal goes to ?l?, the initialization is performed. reset operation is executing during ?l? state of resb. -9- NJU6655 ver.2004-03-05 no. symbol i/o function 11 12 cs 1 b cs 2 i chip select terminal. data input/output are available during cs 1 b=?l? and cs 2 =?h?. 18 rdb (e) i - 10 - NJU6655 ver.2004-03-05 no. symbol i/o function 6 fr i/o lcd alternating current signal i/o terminal. m/s=?h? : output m/s=?l? : input 4 ,9 sync i/o lcd synchronizing current signal i/o terminal. m/s=?h? : output m/s=?l? : input lcd display blanking control terminal. m/s=?h? : output terminal. display ?on? = ?h?, display ?off? = ?l? m/s=?l? : input terminal. external control. refer to the following table. dofb instruction h l display on on off display off off off 8 dofb i/o 81 irs i internal feedback resistor select irs=?h? : internal feedback irs=?l? : external feedback resistor this setting is effective in the master operation. it is ineffective in the slave operation but should be fixed to ?h? or ?l?. 5 frs o the output terminal for the static drive. this terminal is used in conjunction with the sync terminal. 89 to 120 c 31 to c 0 o lcd driving signal output terminals. -common output terminals : c 0 to c 63 -segment output terminals : s 0 to s 159 common output terminals the following output voltages are selected by the combination of alternating (fr) signal and common scanning data. scan data fr output voltage h v 5 h l v dd h v 1 l l v 4 122 to 124, 131 to 284, 2 91 to 293 s 0 to s 159 o segment output terminals the following output voltages are selected by the combination of alternating (fr) signal and display data in the ram. output voltage ram data fr normal reverse h v dd v 2 h l v 5 v 3 h v 2 v dd l l v 3 v 5 2 94 to 325 c 32 to c 63 o 121,326 comm o com output terminals for the indicator. both terminals output the same signal. leave these open if they are not used. 3 test 1 o maker test only. normally open. 79 test 2 i maker test only. this terminal must connect to v ss . -11- NJU6655 ver.2004-03-05 functional description (1) description for each blocks (1-1) busy flag (bf) during internal operation, the lsi is being busy and can?t accept any instructions except ?status read?. the bf data is output through d 7 terminal by the ?status read? instruction. when the cycle time (tcyc) mentioned in the ?ac characteristics? is satisfied, the bf check isn?t required after each instruction, so that mpu processing performance can be improved. (1-2) initial display line register the initial display line register assigns a ddram line address, which corresponds to com 0 by ?initial display line set? instruction. it is used for not only normal display but also vertical display scrolling and page switching without changing the contents of the ddram. however, the 65 th address for icon display can?t be assigned for initial display line address. (1-3) line counter the line counter provides a ddram line address. it initializes its contents at the switching of frame timing signal (fr), and also counts-up in synchronization with common timing signal. (1-4) column address counter the column address counter is an 8-bit preset counter, which provides a ddram column address, and it is independent of below-mentioned page address register. it will increment (+1) the column address whenever ?display data read? or ?display data write? instructions are issued. however, the counter will be locked when no-existing address above a0 h are addressed. the count-lock will be able to be released by the ?column address set? instruction again. the counter can invert the correspondence between the column address and segment driver direction by means of ?adc set? instruction. (1-5) page address register the page address register provides a ddram page address. the last page address ?8? should be used for icon display because the only d 0 is valid. (1-6) display data ram (ddram) the ddram contains 10,400-bit, and stores display data, which are 1-to-1 correspondents to lcd panel pixels. when normal display mode, the display data ?1? turns on and ?0? turns off lcd pixels. when inverse display mode, ?1? turns off and ?0? turns on. - 12 - NJU6655 ver.2004-03-05 page address data display pattern line address common driver d0 00 h c56 d1 01 c57 d2 02 c58 d3 03 c59 d4 04 c60 d5 05 c61 d6 06 c62 d3,d2,d1,d0 (0,0,0,0) d7 page 0 07 c63 d0 08 c0 d1 09 c1 d2 0a c2 d3 0b c3 d4 0c c4 d5 0d c5 d6 0e c6 d3,d2,d1,d0 (0,0,0,1) d7 page 1 0f c7 d0 10 c8 d1 11 c9 d2 12 c10 d3 13 c11 d4 14 c12 d5 15 c13 d6 16 c14 d3,d2,d1,d0 (0,0,1,0) d7 page 2 17 c15 d0 18 c16 d1 19 c17 1a c18 : : : : : : : : : : : : : : : : : : : : 36 c46 d6 37 c47 d7 38 c48 d0 39 c49 d1 3a c50 d2 3b c51 d3 3c c52 d4 3d c53 d6 3e c54 d3,d2,d1,d0 (0,1,1,1) d7 page 7 3f c55 (1,0,0,0) d0 page 8 comm* d0="0" 00 01 02 03 04 05 06 9e 9f column address adc d0="1" 9f 9e 9d 9c 9b 9a 99 01 00 segment drivers 0 1 2 3 4 5 6 - - - - - - - - - - - - - - - - 158 159 for example the initial display is 08 h . fig.1 display data ram (ddram) map * : comm is independent of the ?initial display line set? instruction and always corresponds to the 65 th line. -13- NJU6655 ver.2004-03-05 (1-7) common direction register the common direction register is selected by the "partial select" and "common direction register set" instructions as shown in table 1. when using the partial display function, the com 0 - com 15 and com 48 - com 63 terminals cannot be used. table 1. common direction partial select common direction register set common drivers pad no. 114 83 309 278 d 0 d 3 pin name c 0 c 31 c 63 c 32 0 0 com 0 com 31 com 63 com 32 0 1 com 63 com 32 com 0 com 31 pad no. 98 83 293 278 pin name c 16 c 31 c 47 c 32 1 0 com 16 com 31 com 47 com 32 1 1 com 47 com 32 com 16 com 31 (1-8) reset circuit the reset circuit initializes the lsi to the following status by using of the reset signal into the resb terminal. -reset status using the resb terminal: 1. display off 2. normal display (non-inverse display) 3. adc select : normal mode (d 0 ="0") 4. power control register clear : d 2 ,d 1 ,d 0 =?0,0,0? 5. serial interface register clear 6. lcd bias select : d 1 ,d 0 =?0,0?(1/9 bias) 7. power save reset 8. entire display off : normal mode 9. internal oscillation circuit stop 10.partial select : d 0 =?0?(1/65 duty) 11.static indicator off static indicator register : d 1 ,d 2 =?0,0? 12.read modify write off 13.initial display line address : 00 h 14.column address : 00 h 15.page address : 0 page 16.common direction register : d 3 =?0?(normal) 17.feedback resistors ratio : d 2 ,d 1 ,d 0 =?0,0,0? 18.evr mode off and evr register: d 5 ,d 4 ,d 3 ,d 2 ,d 1 ,d 0 =?1,0,0,0,0,0? 19.n-line inverse drive register : d 3 ,d 2 ,d 1 ,d 0 =?0,0,0,0?(n-line inverse reset) 20.test mode reset (test mode 1 and test mode 2) the res terminal should be connected to mpu?s reset terminal, and the reset operation should be executed at the same timing of the mpu reset. as described in the ?bus timing characteristics?, it is necessary to input 1.5us(min.) or over ?l? level signal into the res terminal in order to carry out the reset operation. the lsi will return to normal operation after about 1.5us(max.) from the rising edge of the reset signal. the reset operation by resb="l" initializes each register setting as above reset status, but the internal oscillation circuit and output terminals (d 0 to d 7 ) are not affected. the reset operation is necessary to avoid malfunctions. note 1) the ?reset? instruction in table.4 can?t be substituted for the reset operation by using of the res terminal. it executes above-mentioned only 11 to 20 items. note 2) the reset terminal is susceptible to external noise, so design pcb layout in consideration for the noise. note 3) in case of using external power supply for lcd driving voltage, the resb terminal is required to be being ?l? level when the external power supply is turned-on. - 14 - NJU6655 ver.2004-03-05 (1-9) lcd driving circuits (a) common and segment drivers lcd drivers consist of 64-common drivers, 160-segment divers and 1-icon-common driver. as shown in ? lcd driving waveform?, lcd driving waveforms are generated by the combination of display data, common timing signal and internal fr timing signal. (b) display data latch circuit the display data latch circuit temporally stores 160-bit display data transferred from the ddram in the synchronization with the common timing signal, and then it transfers these stored data to the segment drivers. ?display on/off?, ?inverse display on/off? and ?entire display on/off? instructions control only the contents of this latch circuit, they can?t change the contents of the ddram. in addition, the lcd display isn?t affected by the ddram accuses during its displaying because the data read-out timing from this latch circuit to the segment drivers is independent of accessing timing to the ddram. (c) line counter and latch signal or latch circuits the clock line counter and latch signal to the latch circuits are generated from the internal display clock (cl). the line address of display data ram is renewed synchronizing with display clock (cl). 160bits display data are latched in display latch circuits synchronizing with display clock, and then output to the lcd driving circuits. the display data transfer to the lcd driving circuits is executed independently with ram access by the mpu. (d) display timing generator the display timing generates the timing signal for the display system by combination of the master clock cl and driving signal fr ( refer to fig.2 ) the frame signal fr and lcd alternative signal generate lcd driving waveform on the 2-frame alternative driving method or the n-line inverse driving method. -15- NJU6655 ver.2004-03-05 (e) common timing generation the common timing is generated by display clock cl (refer to fig.2) fig.2-1 2-frame alternating drive mode fig.2-2 n-line inverse drive mode ( n=7, line inverting register sets to 6) 64 65 1 2 3 4 5 6 7 8 cl fr c0 c1 sn v dd v 1 v 4 v 5 v dd v 1 v 4 v 5 v dd v 2 v 3 v 5 62 63 64 65 1 2 3 4 5 ram data 64 65 1 2 3 4 5 6 7 8 cl fr c0 c1 sn v dd v 1 v 4 v 5 v dd v 1 v 4 v 5 v dd v 2 v 3 v 5 62 63 64 65 1 2 3 4 5 ram data - 16 - NJU6655 ver.2004-03-05 (f) oscillator this is the low power consumption cr oscillator which provides the display clock and voltage converter timing clock. (g) internal power circuits the internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step evr and voltage followers. the optimum values of the external passive components for the internal power circuits, such as capacitors for v 1 to v 5 terminals and feed back resistors for vr terminal, depend on lcd panel size. therefore, it is necessary to evaluate the actual lcd module with these external components in order to determine the optimum values. each portion of the internal power circuits is controlled by ?power control set? instruction as shown in table.2. in addition, the combination of power supply circuits is described in table.3. table.2 power control set status portions ?1? ?0? d 2 voltage converter on off d 1 voltage regulator on off d 0 voltage followers on off table.3 power supply combinations status d 2 d 1 d 0 voltage converter voltage regulator voltage followers external voltage capacitor terminals 1) using all internal power circuits 1 1 1 on on on v ss2 use 2) using voltage regulator and voltage followers 0 1 1 off on on v out ,v ss2 open 3) using voltage followers 0 0 1 off off on v out ,v 5 ,v ss2 open 4) using only external power supply 0 0 0 off off off v out ,v 1 ~v 5 open * capacitor input terminals: c1+, c1-, c2+, c2-, c3- * do not use other combinations except examples in table.3. the internal lcd power supply is designed to drive small lcd panels such as cellular phones. thus, if the ic is used to drive a large panel, make sure whether it works with the internal power supply or needs an external power supply. the selections of external components for the lcd bias circuit, the voltage booster and the feedback loop depend on panel sizes, so make sure what are the best values in the particular application. -17- NJU6655 ver.2004-03-05 power supply applications power control instruction d 2 : boost circuit d 1 : voltage regulator d 0 : voltage follower (1) internal power supply example. (2) only v out supply from outside example. all of the internal booster, voltage regulator, internal voltage regulator, voltage follower using voltage follower using. (d 2 ,d 1 ,d 0 ) = (1,1,1) (d 2 ,d 1 ,d 0 ) = (0,1,1) (3) vout and v5 supply from outside example. (4) external power supply example. internal voltage follower using. all of v 1 to v 5 and v out supply from outside (d 2 ,d 1 ,d 0 ) = (0,0,1) (d 2 ,d 1 ,d 0 ) = (0,0,0) : these switches should be open during the power save mode. note) : when using the voltage follower circuit, external resistors may be necessary to stabilize v 1 ,v 2 ,v 3 and v 4 voltages. v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd v 5 vr + + + + + + c1 - c1 + c3 - c2 + c2 - + + v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd vr v 5 + + + + + v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 + + + + v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 - 18 - NJU6655 ver.2004-03-05 (2) instruction set the NJU6655 distinguishes the signal on the data bus d 0 to d 7 as an instruction by combination of a0 , rdb and wrb(r/w). the decode of the instruction and execution performs with only high speed internal timing without relation to the external clock. therefore no busy flag check required normally. in case of serial interface, the data input as msb(d 7 ) first serially. the table. 4-1,4-2 shows the instruction codes of the NJU6655 . table. 4-1 instruction table (*: don?t care) instruction code instruction a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description (a) display on/off 0 1 0 1 0 1 0 1 1 1 0/1 lcd display on/off d 0 =0:off d 0 =1:on (b) initial display line set 0 1 0 0 1 line address determine the display line of ram to com 0 (c) page address set 0 1 0 1 0 1 1 page address set the page of dd ram to the page address register column address set upper order 4bits 0 1 0 0 0 0 1 upper order column address set the upper order 4 bits column address to the register (d) column address set lower order 4bits 0 1 0 0 0 0 0 lower order column address set the lower order 4 bits column address to the register (e) status read 0 0 1 status 0 0 0 0 read out the internal status (f) write display data 1 1 0 write data write the data into the display data ram (g) read display data 1 0 1 read data read the data from the display data ram (h) adc select 0 1 0 1 0 1 0 0 0 0 0/1 set the dd ram vs segment d 0 =0 :normal d 0 = 1:inverse (i) normal or inverse of on/off set 0 1 0 1 0 1 0 0 1 1 0/1 inverse the on and off display d 0 =0 :normal d 0 = 1:inverse (j) static drive on /normal display 0 1 0 1 0 1 0 0 1 0 0/1 whole display turns on d 0 =0: normal d 0 =1: whole disp. on (k) lcd bias select 0 1 0 1 0 0 1 0 0 bias select the bias (l) read modify write 0 1 0 1 1 1 0 0 0 0 0 increment the column address register when writing but no-change when reading (m) end 0 1 0 1 1 1 0 1 1 1 0 release from the read modify write mode (n) reset 0 1 0 1 1 1 0 0 0 1 0 initialize the internal circuits (o) common direction select 0 1 0 1 1 0 0 0/1 * * * set the scanning order of common drivers to the register d 3 =0 : normal, d 3 =1 : inverse (p) power control set 0 1 0 0 0 1 0 1 operating mode set the status of internal power circuits (q) feedback resistor ratio set 0 1 0 0 0 1 0 0 resistor ratio set the status of internal resistors ratio (rb/ra) -19- NJU6655 ver.2004-03-05 table. 4-2 instruction table (*: don?t care) instruction code instruction a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description evr mode set 0 1 0 1 0 0 0 0 0 0 1 set evr mode (r) evr register set 0 1 0 * * setting data set the v 5 output level to the evr register static indicator on/off 0 1 0 1 0 1 0 1 1 0 0/1 d 0 =0 : off, d 0 =1 : on (s) static indicator register set 0 1 0 * * * * * * mode set static indicator register (t) pawer save 0 1 0 1 0 1 0 1 0 0 0/1 d 0 =0 : standby mode d 0 =1 : sleep mode (u) pawer save reset 0 1 0 1 1 1 0 0 0 0 1 release from the pawer save mode (v) n-line inverse drive register set 0 1 0 0 0 1 1 number of inverse lines set the number of inverse drive line (w) n-line inverse drive reset 0 1 0 1 1 1 0 0 1 0 0 release the line inverse drive (x) partial select 0 1 0 1 0 1 0 0 0 1 0/1 d 0 =0 : off (1/65 duty) d 0 =1 : on (1/33 duty) (y) internal oscillation circuit on 0 1 0 1 0 1 0 1 0 1 1 start the operation of the internal oscillation circuit (z) nop 0 1 0 1 1 1 0 0 0 1 1 - 20 - NJU6655 ver.2004-03-05 (2-1) explanation of instruction code (a) display on/off this instruction selects display turn-on or turn-off regardless of the contents of the ddram. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d d 0: display off 1: display on (b) initial display line set this instruction specifies the ddram line address which corresponds to the com 0 position. by means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth display scrolling will be enabled. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 a 5 a 4 a 3 a 2 a 1 a 0 a 5 a 4 a 3 a 2 a 1 a 0 line address (hex) 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 1 : : 1 00 01 : : 3f (c) page address set in order to access to the ddram for writing or reading display data, both ?page address set? and ?column address set? instructions are required before accessing. the last page address ?8? should be used for icon display because the only d 0 is valid. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 page 0 0 : : 1 0 0 : : 0 0 0 : : 0 0 1 : : 0 0 1 : : 8 -21- NJU6655 ver.2004-03-05 (d) column address set as above-mentioned, in order to access to the ddram for writing or reading display data, it is necessary to execute both ?page address set? and ?column address set? before accessing. the 8-bit column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column address register. once the column address is set, it will automatically increment (+1) whenever the ddram will be accessed, so that the ddram will be able to be continuously accessed without ?column address set? instruction. the column address will stop increment and the page address will not be changed when the last address 9f h is addressed. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 a 7 a 6 a 5 a 4 upper 4-bit 0 1 0 0 0 0 0 a 3 a 2 a 1 a 0 lower 4-bit a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address (hex) 0 0 : : 1 0 0 : : 0 0 0 : : 0 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 1 : : 1 00 01 : : 9f (e) status read this instruction reads out the internal status regarding ?busy flag?, ?adc select?, ?display on/off? and ?reset?. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset 0 0 0 0 busy : when d 7 is ?1?, the lsi is being busy and can?t accept any instructions. adc : it shows the correspondence between the column address and segment drivers. when d 6 is ?0?, the column address (159-n) corresponds to segment driver n. when d 6 is ?1?, the column address (n) corresponds to segment driver n. please be careful that read out data is opposite of ?adc select? instruction data. on/off : it shows display on or off status. when d 5 is ?0?, the lsi is in display-on status. when d 5 is ?1?, the lsi is in display-off status. please be careful that read out data is opposite of ?display on/off? instruction data. reset : it shows reset status. when d 4 is ?0?, the lsi is in normal operation. when d 4 is ?1?, the lsi is during reset operation. (f) display data write this instruction writes display data into the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without ?column address set? instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data - 22 - NJU6655 ver.2004-03-05 (g) display data read this instruction reads out the display data stored in the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is read out by this instruction, so that this instruction can be continuously issued without ?column address set? instruction. after the ?column address set? instruction, a dummy read will be required, please refer to the (4-4). in case of using serial interface mode, this instruction can?t be used. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data (h) adc select this instruction selects segment driver direction. the correspondence between the column address and segment driver direction is shown in fig.1. this function reduces the restrictions on the ic position of an lcd module. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 d d 0: clockwise output (normal) segment driver s 0 to s 159 1: counterclockwise output (inverse) segment driver s 159 to s 0 (i) inverse display on/off this instruction inverses the status of turn-on or turn-off of entire lcd pixels. it doesn?t change the contents of the ddram. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 1 d d 0: normal ram data "1" correspond to "on" 1: inverse ram data "0" correspond to "on" (j) entire display on/off this instruction turns on entire lcd pixels regardless the contents of the ddram. it doesn?t change the contents of ddram. this instruction should be performed prior to the "inverse display on/off" instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d d 0: normal display 1: whole display turns on (k) bias select this instruction selects lcd bias value. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 1 0 0 a 1 a 0 a 1 a 0 lcd bias 0 0 1 1 0 1 0 1 1/9 1/7 1/5 prohibited* * : because it may malfunction-operate, do not set (d 1 ,d 0 ) = (1,1). -23- NJU6655 ver.2004-03-05 (l) read modify write this instruction controls column address increment. by using of this instruction, the column address can?t increment when read operation but it can increment when write operation. this status will be continued until the below-mentioned ?end? instruction will be issued. this instruction can reduce the load of mpu, during the display data in specific ddram area is repeatedly changed for cursor blink or others. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 0 0 note) in this "read modify write" mode, out of display data "read" / "write", any instructions except "column address set" can be executed. - the sequence of cursor blink display pa g e address set finish? set to the start address of curso r display start the read modif y write n o yes repeating column address set read modif y write dumm y rea d data rea d data write the data is i g nored dumm y rea d data rea d data write dumm y rea d data rea d en d data write data inverse b y mpu column counter doesn?t increase column counter increase column counter doesn?t increase column counter doesn?t increase column counter increase column counter doesn?t increase column counter doesn?t increase column counter increase end the read modif y write - 24 - NJU6655 ver.2004-03-05 (m) end the ?end? instruction cancels the read modify write mode and makes the column address return to the initial value just before ?read modify write? is started. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 1 1 1 0 return column n n+1 n+2 n+3 - - - - n+m n address read modify write end (n) reset this instruction reset the lsi to the following status, however it doesn?t change the contents of the ddram. please be careful that it can?t be substituted for the reset operation by using of the resb terminal. reset status by ?reset? instruction: 1: static indicator register : d 1 ,d 0 = ?0,0? 2: read modify write off 3: initial display line address : 00 h 4: column address : 00 h 5: page address : 0 page 6: common direction register : d 3 =?0?(normal mode) 7: feedback resistors ratio : d 2 ,d 1 ,d 0 = ?0,0,0? 8: evr mode off and evr register : d 5 ,d 4 ,d 3 ,d 2 ,d 1 ,d 0 = ?1,0,0,0,0,0? 9: n-line inverse drive register : d 3 ,d 2 ,d 1 ,d 0 = ?0,0,0,0? 10: test mode reset (test mode 1 and test mode 2) the dd ram is not affected of this initialization. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 0 (o) common driver direction select this instruction selects common driver direction. please refer to (1-7) common driver direction for more detail. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 0 0 d 3 * * * (*: don?t care) d 3 0: normal common driver direction (c 0 to c 63 ) or (c 16 to c 47 ) 1: inverse common driver direction (c 63 to c 0 ) or (c 47 to c 16 ) -25- NJU6655 ver.2004-03-05 (p) power control set this instruction controls the status of internal power circuits. please refer to the (1-9) lcd driving circuits (g) internal power circuits for more detail. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 1 a 2 a 1 a 0 a 2 0: voltage converter off 1: voltage converter on a 1 0: voltage regulator off 1: voltage regulator on a 0 0: voltage followers off 1: voltage followers on note) the internal power supply must be off when external power supply using. * the wait time depends on the c 4 to c 8 , c out capacitors, and v dd and v lcd voltage. therefore it requires the actual evaluation using the lcd module to get the correct time. (q) feedback resistor ratio set this instruction is used to determine the internal feedback resistor ratio. please refer to the (3-2) voltage adjust circuits for more detail. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 a 2 a 1 a 0 a 2 a 1 a 1 internal resistor ratio 1+(rb/ra) v lcd 1+(rb/ra) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4.5 5.0 5.5 6.0 6.5 7.0 7.6 8.1 minimum : : : : : : maximum - 26 - NJU6655 ver.2004-03-05 (r) evr set 1) evr mode set this instruction sets the lsi into the evr mode, and it is always used by the combination with ?evr register set?. the lsi can?t accept any instructions except the ?evr register set? during the evr set mode. this mode will be released after the ?evr register set? instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 0 0 0 1 2) evr register set this instruction sets 6-bit data into the evr register to determine the output voltage ?v 5 ? of the internal voltage regulator. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 * * a 5 a 4 a 3 a 2 a 1 a 0 (*: don?t care) a 5 a 4 a 3 a 2 a 1 a 0 v lcd 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 1 : : 1 minimum : : : maximum (s) static indicator 1) static indicator on/off this instruction selects static indicator turn-on or turn-off, and it is always used by the combination with the ? static indicator register set?. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 0 d d 0: static indicator off 1: static indicator on 2) static indicator register set a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 * * * * * * a 1 a 0 (*: don?t care) a 1 a 0 indicator display status 0 0 1 1 0 1 0 1 off on (blink at 1.0s intervals) on (blink at 0.5s intervals) on (turn on at all time) -27- NJU6655 ver.2004-03-05 (t) power save this instruction sets the lsi into the power save mode. this instruction is reducing operating current as well as static operations. the internal status and the contents of the ddram will be remained just before the ?power save? instruction. in addition, the ddram can be accessed during the power save mode. there are two power save modes, sleep mode and standby mode. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 0 0 d d 0: standby mode 1: sleep mode - 28 - NJU6655 ver.2004-03-05 (v) n-line inverse drive register set this instruction specifies the number of n-line. please refer to the (1-9)lcd driving circuits (e)common timing generation fig.2-1, fig.2-2 for more detail. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 inverse lines 0 0 0 : 1 1 0 0 0 : 1 1 0 0 1 : 1 1 0 1 0 : 0 1 -(*) 2 3 : 15 16 ( *) 2-frame alternating drive m ode. (w) n-line inverse drive reset this instruction releases n-line inversion, but does not change the contents of the n-line register. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 1 0 0 (x) patial select this instruction starts the partial mode operation. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 1 d d 0: 1/65 duty (partial select off) 1: 1/33 duty (partial select on) display structure by partial select on / off partial select off (1/65 duty) partial select on (1/33 duty) com 0 ~com 7 com 0 ~com 7 com 8 ~com 15 com 8 ~com 15 com 16 ~com 23 com 16 ~com 23 com 24 ~com 31 com 24 ~com 31 com 32 ~com 39 com 32 ~com 39 com 40 ~com 47 com 40 ~com 47 com 48 ~com 55 com 48 ~com 55 com 56 ~com 63 com 56 ~com 63 comm 64com+1 comm 32com+1 160seg 160seg active display-block -29- NJU6655 ver.2004-03-05 (y) internal oscillation circuit on this setting is effective when m/s=?1? and cls=?1?. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 0 1 1 (z)nop non operation. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 1 - 30 - NJU6655 ver.2004-03-05 (3) internal power circuits (3-1) voltage converter the voltage converter generates maximum 4x boosted negative-voltage from the voltage between v dd and v ss2 . the boosted voltage is output from the v out terminal. the internal oscillator is required to be operating when using this converter, because the divided signal provided from the oscillator is used for the internal timing of this circuit. the boosted voltage between v dd and v out must not exceed 18.0v. the voltage converter requires external capacitors for boosting as shown in below. the boosted voltage and v dd , v ss2 2x boost 3x boost 4x boost example for connecting the capacitors 4x boost 3x boost 2x boost + + + v ss2 c1 - c1 + c3 - c2 + c2 - v out + + + v ss2 c1 - c1 + c3 - c2 + c2 - v out + + v ss2 c1 - c1 + c3 - c2 + c2 - v out v dd =+3v v ss2 =0v v out =-3v v out =-6v v out =-9v -31- NJU6655 ver.2004-03-05 (3-2) voltage adjust circuits the voltage adjust circuits is composed of the reference voltage circuit, 64-step e.v.r. and feedback resistors. the adjust circuits produces the lcd driving voltage v 5 on the v 5 terminal, using the v out voltage supplied from the internal booster. (a) using internal feedback resistors lcd contrast can be fine-tuned by adjusting the v 5 voltage through setting the internal feedback resistors and the e.v.r. and the v 5 voltage is calculated from the foemula (1), where |v 5 | < |v out |. v lcd = v dd -v 5 - - - - - (1) = (1+(rb/ra)) x v con [v con = (evr) x (v reg )] = (1+(rb/ra)) x (evr) x v reg [evr = (n+99) / 162] v lcd : lcd driving voltage v con : contrast control voltage v reg : reference voltage ra,rb : feedback resistors n : e.v.r. setting value fig.3-1 voltage adjust circuits (using internal feedback resistors) the v reg is the regulated voltage with temperature coefficient, as follows. temperature coefficient v reg internal power supply 0.05[%/c] (typ.) 2.11[v] (typ.) the v 5 is adjusted in 64-step by setting 6-bit data into the e.v.r. register, as follows. e.v.r. register e.v.r. value v lcd 00 h (0,0,0,0,0,0) (99/162) minimum 01 h (0,0,0,0,0,1) (100/162) : 02 h (0,0,0,0,1,0) (101/162) : : : : : : : : : : : : : 3d h (1,1,1,1,0,1) (160/162) : 3e h (1,1,1,1,1,0) (161/162) : 3f h (1,1,1,1,1,1) (162/162) maximum v con (v reg x evr) internal ra internal rb v 5 v dd + - v lcd v out - 32 - NJU6655 ver.2004-03-05 the ratio of the ra and rb (ra/rb) is selected out of 8 options by the "feedback resistor set" instruction. the register of feedback resistor 1+(rb/ra) v lcd 00 h (0,0,0) 4.5 minimum 01 h (0,0,1) 5.0 : 02 h (0,1,0) 5.5 : 03 h (0,1,1) 6.0 : 04 h (1,0,0) 6.5 : 05 h (1,0,1) 7.0 : 06 h (1,1,0) 7.6 : 07 h (1,1,1) 8.1 maximum * : the resistance of the feedback resistors has a certain amount of error. if it may impact on the lcd contrast external feedback resistors should be considered. (b) using external feedback resistors when irs="l", the v 5 voltage can be adjusted by the external feedback resistors. and the e.v.r. function is applied in combination, and fine-tunes the lcd contrast through software. the v 5 voltage is calculated from the formula (2), where |v 5 | < |v out |. v lcd = v dd -v 5 - - - - - (2) = (1+(rb/ra)) x v con [v con = (evr) x (v reg )] = (1+(rb/ra)) x (evr) x v reg [evr = (n+99) / 162] v lcd : lcd driving voltage v con : contrast control voltage v reg : reference voltage ra,rb : feedback resistors n : e.v.r. setting value fig.3-2 voltage adjust circuits (using external feedback resistors) * : when using either the internal feedback resistors or e.v.r. or both, the lcd voltage generator and the buffer amplifiers must be activated. * : the vr terminal is only used for the external feedback resistors. this must be open when using the internal feedback resistors. v con (v reg x evr) external ra external rb v 5 v dd + - v lcd v out vr -33- NJU6655 ver.2004-03-05 - 34 - NJU6655 ver.2004-03-05 (3-3) lcd driving voltage generation circuits the lcd driving bias voltage of v 1 ,v 2 ,v 3 ,v 4 are generated internally by dividing the v lcd (v lcd =v dd -v 5 ) voltage with the internal bleeder resistance. and it is supplied to the lcd driving circuits after the impedance conversion with voltage follower circuit. as shown in fig 4, five capacitors are required to connect to each lcd driving voltage terminal for voltage stabilizing. and the value of capacitors c 4 , c 5 , c 6 , c 7 , and c 8 are determined depending on the actual lcd panel display evaluation. using the internal power supply using the external power supply fig.4 lcd driving voltage generation circuits *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *2 following connection of v out is required when external power supply using. (1): when v ss > v 5 --- v out =v 5 (2): when v ss < v 5 --- v out =v ss v ss c1 - c1 + c3 - c2 + vr v out c2 - n ju6655 v 5 v dd v 1 v 2 v 3 v 4 v 5 external voltage generator + + v ss v ss2 c1 - c1 + c3 - c2 + vr v out c2 - n ju6655 v 5 v dd v 1 v 2 v 3 v 4 v 5 + + + + + c 4 c 5 c 6 c 7 c 8 c 1 c 3 c 2 c out r2 r1 r3 *1 *2 reference set up value v lcd =v dd -v 5 =7.0 to 10.5v c out c 1 ~c 3 , c 8 c 4 ~c 7 r1 r2 r3 ~1.0uf ~1.0uf 0.1 ~ 0.47uf 225k ? 112k ? 1.063m ? + ( 2 ) ( 1 ) -35- NJU6655 ver.2004-03-05 (4) mpu interface (4-1) interface type selection NJU6655 interfaces with mpu by 8-bit bidirectional data bus (d 7 to d 0 ) or serial (si:d 7 ). the 8 bit parallel or serial interface is determined by a condition of the p/s terminal connecting to "h" or "l" level as shown in table 5. in case of the serial interface, status and ram data read out operation is impossible. table.5 relation between p/s terminal and each i/o terminal p/s type cs 1 b a0 rdb wrb c86 si(d 7 ) scl(d 6 ) d 0 ~ d 5 h parallel cs 1 b a0 rdb wrb c86 d 7 d 6 d 0 ~ d 5 l serial cs 1 b a0 - - - si scl hi-z ?hi-z? : hi-impedance ?-? : they should be fixed to ?h? or ?l?. parallel interface the NJU6655 interfaces to 68 or 80 type mpu directly when the parallel interface (p/s="h") is selected. 68 type mpu or 80 is determined by the condition of c86 terminal connecting to "h" or "l" as shown in table 6. table.6 relation between c86 terminal and each i/o terminal c86 type cs 1 b a0 rdb wrb d 0 ~ d 7 h 68 type mpu cs 1 b a0 e r/w d 0 ~ d 7 l 80 type mpu cs 1 b a0 rdb wrb d 0 ~ d 7 (4-2) discrimination of data bus signal the NJU6655 discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rdb,wrb) signals as shown in table 7. table.7 relation between a0 terminal and 68/80 type terminal common 68 type 80 type a0 r/w rdb wrb function h h l h read display data h l h l write display data l h l h status read l l h l write into the register(instruction) - 36 - NJU6655 ver.2004-03-05 (4-3) serial interface (p/s="l") serial interface circuits consist of 8 bits shift register and 3 bits counter. si and scl input are activated when the chip select terminal cs 1 b set to "l", cs 2 set to "h"and p/s terminal set to "l". the 8 bits shift register and 3 bits counter are reset to the initial condition when the chip is not selected. the data input from si terminal is msb first like as the order of d 7 ,d 6 ,- - - - d 0 , and the data are entered into the shift register synchronizing with the rise edge of the serial clock scl. the data in the shift register are converted to parallel data at the 8th serial clock rise edge input. discrimination of the display data or instruction of the serial input data is executed by the condition of a0 at the 8th serial clock rise edge. a0="h" is display data and a0="l" is instruction. when resb terminal becomes "l" or cs 1 b terminal becomes "h" (cs 2 terminal becomes "l") before 8th serial clock rise edge, NJU6655 recognizes them as a instruction data incorrectly. therefore a unit of serial data must be structured by 8-bit. the time chart for the serial interface is shown in fig. 5. to avoid the noise trouble, the short wiring is required for the scl input. note) the read out function, such as the status or ram data read out, is not supported in this serial interface. fig.5 signal chart of serial interface cs 1 b si scl a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 1 2 3 4 5 6 7 8 9 10 cs 2 -37- NJU6655 ver.2004-03-05 (4-4) access to the display data ram and internal register the NJU6655 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between mpu and the display data ram or internal register. for example, when the mpu reads out the data from the display data ram, the read out data in the data read cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read cycle. when the mpu writes the data into the display data ram, the data is held in the bus-holder, then it is written into the display data ram by the next data write cycle. therefore high speed data transmission between mpu and NJU6655 is available because of it is not limited by the tacc and tds as display data ram access time and is limited by the system cycle time (r) or (w). if the cycle time is not be kept in the mpu operation, nop should be inserted to the system instead of the waiting operation. the read out operation does not read out the data in the pointed address just after the address set operation. and second read out operation can read out the data correctly from the pointed address. therefore, one dummy read operation is required after address setting or write cycle as shown in fig. 6. the example of read modify write operation is mentioned in (2-1) instruction (l)the sequence of inverse display. write operation read operation fig.6 relation between display data write/read and internal timing (4-5) chip select cs 1 b, cs 2 are chip select terminals. in case of cs 1 b="l" and cs 2 =?h?, the interface with mpu is available. in case of cs 1 b=?h? or cs 2 =?l?, the d 0 to d 7 are high impedance and a0, rdb, wrb, d 7 (si) and d 6 (scl) inputs are ignored. if the serial interface is selected when cs 1 b=?h? or cs 2 =?l?, the shift register and the counter are reset. however, the reset is always operated in any conditions of cs 1 b and cs 2 . cpu wrb internal timing data n n +1 n +2 n +3 bus holde r n n +1 n +2 n +3 wrb cpu wrb rdb data n n n n+1 address set n dumm y read data read n data read n+1 internal timing wrb rdb column address n n +1 n +2 bus holde r n n n+1 n+2 - 38 - NJU6655 ver.2004-03-05 absolute maximumn ratings (ta=25c) parameter symbol ratings unit supply voltage (1) v dd -0.3 to +7.0 v supply voltage (2) ( when using 3x voltage converter ) ( when using 4x voltage converter ) vss 2 -7.0 to +0.3 -6.0 to +0.3 -4.5 to +0.3 v supply voltage (3) v 5 ,v out -18.0 to +0.3 v supply voltage (4) v 1 ,v 2 ,v 3 ,v 4 v 5 to +0.3 v input voltage v in -0.3 to v dd + 0.3 v output voltage v out -0.3 to v dd + 0.3 v operating temperature t opr -30 to +80 c -55 to +100 storage temperature (tcp) (chip) t stg -55 to +125 c note 1) v ss2 , v 1 to v 5 , v out voltage values are specified as v dd = 0v. note 2) the relation of v dd > v 1 > v 2 > v 3 > v 4 > v 5 >v out ; v dd >v ss > v out must be maintained. in case of inputting external lcd driving voltage, lcd drive voltage should start supplying to NJU6655 at the mean time of turning on v dd power supply or after turned on v dd . in use of the voltage boost circuit, the condition that the supply voltage : 18v > v dd -v out is necessary. note 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. note 4) decoupling capacitor should be connected between v dd and v ss due to the stabilized operation for the voltage converter. v dd v dd v ss v ss2 , v 1 to v 4 v 5 -39- NJU6655 ver.2004-03-05 dc electrical characteristics (v dd =2.4 to 3.6v, v ss =0v, ta= -30 to 80c) paramet er symbol conditions min typ max unit note 2.4 - 3.6 v power supply (1) v dd recommend possible 2.4 - 5.5 v 5 power supply (2) v ss2 v dd common -6.0 - -2.4 v v 5 v dd common -18 - -4.5 v 1 ,v 2 0.4v 5 - v dd power supply (3) v 3 ,v 4 v dd common v 5 - 0.6v 5 v ?h? level input voltage v ihc1 0.8v dd - v dd v ?l? level input voltage v ilc1 v ss - 0.2v dd v ?h? level output voltage v ohc1 i oh =-0.5ma 0.8v dd - v dd v ?l? level output voltage v olc1 i ol = 0.5ma v ss - 0.2v dd v i li all input terminals -1.0 - 1.0 ua leakage current i lo d 0 to d 7 terminals, hi-z state -3.0 - 3.0 ua r on1 v 5 =-14.0v - 2.0 3.5 k ? driver on-resistance r on2 ta=25c v 5 =-8.0v - 3.2 5.4 k ? 6 stand-by current i ssq - 0.01 5 ua output leakage current i 5q v 5 =-18.0v (v dd common) - 0.01 15 ua input terminal capacitance c in ta=25c - 5 8 pf 7 oscillation frequency f osc v dd =3v,ta=25c 17.0 20.8 24.6 khz display clock frequency f cl external input 4.25 5.20 6.15 khz v dd common, 3-times boost -6.0 - -2.4 input voltage v ss2 v dd common, 4-times boost -4.5 - -2.4 v output voltage v out v dd common -18.0 - - v on-resistance r quad 4-times boost, c 1 -c 3 , c out =1uf v dd =3v, v ss =v ss2 2.5 3.5 k ? adjustment range lcd driving voltage v out2 voltage boost operation off external power supply -18.0 - -6.0 v voltage follower operating voltage v 5 voltage adjustment circuit off external power supply -18.0 - -4.5 v 8 i ddq1 power save mode (sleep mode) 0.01 5.0 i ddq2 power save mode (standby mode) 4 10 ua i dd1 130 operating current i dd2 v dd =3v, v 5 =-11v all com/seg open, without mpu access, checker flag display 35 ua 9 reference voltage v ref ta=25c 2.11 v volta g e booste r temperature coefficient tc v dd =3v -0.05 %/c note 5) although the NJU6655 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with mpu. note 6) r on is the resistance values in supplying 0.1v voltage-difference between power supply terminals (v 1 ,v 2 ,v 3 ,v 4 ) and each output terminals (common / segment). this is specified within the range of operating voltage (2). note 7) apply to a0, d 7 to d 0 , rdb, wrb, cs 1 b, cs 2 , resb, c86 and p/s terminals. note 8) the voltage adjustment circuit controls v 5 within the range of the voltage follower operating voltage. note 9) each operating current shall be defined as being measured in the following condition. - 40 - NJU6655 ver.2004-03-05 power control operating condition symbol d 2 d 1 d 0 voltage converter voltage regulator voltage followers external voltage supply (input terminal) i dd1 1 1 1 on on on use(v ss2 ) i dd2 0 0 0 off off off use(v out ,v 1 v 5 ) idd 1,2 measurement circuits: :i dd1 :i dd2 a NJU6655 + + + v dd vr v 5 c1 + v ss v out c1 - c2 - c3 - c2 + a NJU6655 v out v dd vr v 5 c1 + v ss c1 - c2 - c3 - c2 + v 4 v 1 v 2 v 3 v 4 v 1 v 2 v 3 + -41- NJU6655 ver.2004-03-05 bus timing characteristics - read and write characteristics (80 type mpu) (v ss =0v, v dd =2.4 to 3.6v, ta=-40 to 85c) parameter terminal symbol condition min max unit address hold time t ah8 0 - ns address set up time a0,cs 1 b cs 2 t aw8 0 - ns system cycle time t cyc8 800 - ns control ?l? pulse width (wrb) t cclw 120 - ns control ?l? pulse width (rdb) t cclr 240 - ns control ?h? pulse width (wrb) t cchw 120 - ns control ?h? pulse width (rdb) wrb rdb t cchr 120 - ns data set up time t ds8 80 - ns data hold time t dh8 30 - ns rdb access time t acc8 - 280 ns output disable time d 0 to d 7 t oh8 cl=100pf 10 200 ns input signal rising, falling edge cs 1 b,cs 2 , wrb,rdb, a0,d 0 to d 7 tr, tf 15 ns note 10) each timing is specified based on 0.2xv dd and 0.8xv dd . * : (1) accessed by wrb and rdb signal when cs 1 b="l". (2) accessed by cs 1 b signal when wrb and rdb ="l". (1)wrb,rdb (2)cs 1 b t cyc8 t aw8 t cch t ccl t ah8 t ds8 t dh8 t f t r t acc8 t oh8 a0 (1)cs 1 b (2)wrb,rdb d 0 to d 7 (write) d 0 to d 7 (read) cs 2 =h * * - 42 - NJU6655 ver.2004-03-05 - read and write characteristics (68 type mpu) (v ss =0v, v dd =2.4 to 3.6v, ta=-40 to 85c) parameter terminal symbol condition min max unit address hold time t ah6 0 - ns address set up time a0,cs 1 b cs 2 t aw6 0 - ns system cycle time t cyc6 800 - ns enable ?h? pulse width (read) t ewhr 240 - ns enable ?h? pulse width (write) t ewhw 120 - ns enable ?l? pulse width (read) t ewlr 120 - ns enable ?l? pulse width (write) e(rdb) t ewlw 120 - ns data set up time t ds6 80 - ns data hold time t dh6 30 - ns rdb access time t acc6 - 280 ns output disable time d 0 to d 7 t oh6 cl=100pf 10 200 ns input signal rising, falling edge e(rdb), r/w(wrb), a0,d 0 to d 7 tr, tf 15 ns note 11) each timing is specified based on 0.2xv dd and 0.8xv dd . * : (1) accessed by wrb and rdb signal when cs 1 b="l". (2) accessed by cs 1 b signal when wrb and rdb ="l". t cyc6 t ewh t ewl t aw6 t r t f t ah6 t ds6 t dh6 t acc6 t oh6 cs 2 =h (1)e (2)cs 1 b * (1)cs 1 b (2)e * a0,r/w d 0 to d 7 (write) d 0 to d 7 (read) -43- NJU6655 ver.2004-03-05 - write characteristics (serial interface) (v ss =0v, v dd =2.4 to 3.6v, ta=-40 to 85c) parameter terminal symbol condition min max unit serial clock cycle t scyc 400 - ns scl ?h? pulse width t shw 150 - ns scl ?l? pulse width scl(d 6 ) t slw 150 - ns address set up time t sas 250 - ns address hold time a0 t sah 250 - ns data set up time t sds 150 - ns data hold time si(d 7 ) t sdh 150 - ns t css 250 - ns cs 1 b-scl time cs 1 b,cs 2 t csh 250 - ns input signal rising, falling edge scl(d 6 ),a0, cs 1 b,cs 2 , si(d 7 ) tr,, tf 15 ns note 12) each timing is specified based on 0.2xv dd and 0.8xv dd . t css cs 2 =h t csh t sas t sah t scyc t slw t shw t sds t sdh t f t r cs 1 b a0 scl si - 44 - NJU6655 ver.2004-03-05 - display control timing characteristics (v ss =0v, v dd =2.4 to 3.6v, ta=-40 to 85c) paramet er terminal symbol condition min typ max unit fr delay time fr t dfr cl=50pf - 50 200 ns sync delay time sync t dsnc cl=50pf - 50 200 ns note 13) each timing is specified based on 0.2xv dd and 0.8xv dd . (the delay time is applied to the master operation only.) - reset input timing (v ss =0v, v dd =2.4 to 3.6v, ta=-40 to 85c) paramet er terminal symbol condition min typ max unit reset time t r - - 1.5 us reset ?l? level pulse width resb t rw 1.5 - - us note 14) each timing is specified based on 0.2xv dd and 0.8xv dd . t rw resb t r internal circuit status during reset end of reset cl (out) t dfr fr sync t dsnc -45- NJU6655 ver.2004-03-05 lcd driving waveform s e g 1 s e g 2 s e g 3 s e g 4 1 2 3 4 64 1 2 3 4 5 s e g 0 0 0 65 64 65 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 0 fr v dd v ss v dd v 1 v 2 v 3 v 4 com 0 v 5 v dd v 1 v 2 v 3 v 4 com 1 v 5 v dd v 1 v 2 v 3 v 4 com 2 v 5 v dd v 1 v 2 v 3 v 4 seg 0 v 5 v dd v 1 v 2 v 3 v 4 seg 1 v 5 v dd -v 1 -v 2 -v 3 -v 4 com 0 -seg 0 -v 5 v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 com 0 -seg 1 -v 5 v 5 v 4 v 3 v 2 v 1 - 46 - NJU6655 ver.2004-03-05 application circuit (1) microprocessor interface example the NJU6655 interfaces to 80 type or 68 type mpu directly. and the serial interface also communicate with mpu. * : c86 terminal must be fixed v dd or v ss . 80 type mpu 68 type mpu serial interface c p u a0 a1~a7 res reset c86 p/s vcc gnd decoder NJU6655 vss vdd iorq d0~d7 rd wr a0 cs 1 b d0~d7 rdb wrb resb cs 2 c p u a0 a1~a15 vcc vm a d0~d7 res gnd e r/w reset decoder c86 n ju6655 vdd a0 cs 1 b p/s vss d0~d7 e r/w resb cs 2 c p u a0 a1~a7 vcc port 1 res gnd port 2 reset decoder c86 n ju6655 vdd a0 cs 1 b vdd or gnd si scl p/s vss resb cs 2 -47- NJU6655 ver.2004-03-05 (2) 65 x 320 dots driving application circuits example (common and segment drivers extension by using two of NJU6655 ) lcd panel : 65 x 320 m/s fr cl dofb m/s fr cl dofb n ju6655 maste r n ju6655 slave com seg seg com sy n c sync [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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